CPU Architecture and Performance Architect

Mountain View, California


Employer: Google
Industry: Hardware Engineering
Salary: Competitive
Job type: Full-Time

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 5 years of experience with microprocessor architecture, microarchitecture, performance, and design.
  • Experience with performance modeling, analysis, correlation, and workload characterization.
  • Experience with CPU architecture (e.g., CPU block).
  • Experience with C/C and scripting languages.


Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on Computer Architecture, or a related field.
  • Experience leading CPU/Machine Learning microarchitecture exploration, performance model development, performance analysis, performance correlation, and workload characterization.
  • Knowledge of processor instruction set architecture (e.g., ARM, RISC-V, x86).
  • Knowledge of system software components, such as Linux, drivers, and runtime.


About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Pulling on your technical and leadership expertise, you lead end-to-end research projects in multiple areas of expertise across data center facilities and manage a team of direct reports working on equipment installation, troubleshooting and debugging.

As a CPU Architecture and Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and to deliver Google's advanced SoC products. You will have the opportunity to collaborate with talents in Google's Android applications and Google's world-renowned AI teams to plan and conduct application and benchmark performance analysis and to project their performance at various design phases. Leveraging your CPU-specific knowledge and leadership, you will be guiding junior CPU architects and working with exceptional engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

  • Plan and evaluate ARM's architecture features from both architecture and performance angles.
  • Develop a performance model for performance analysis and microarchitecture study.
  • Define and write CPU subsystem architecture specifications.
  • Lead collaboration with RTL, Design Verification, and Physical Design teams to develop a high performance and efficient CPU implementation.
  • Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage.

Created: 2024-06-29
Reference: 92000157714784966
Country: United States
State: California
City: Mountain View


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