Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
• Experience with a scripting language such as Perl or Python.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience implementing Camera ISP image processing blocks, Machine Learning IPs, or other multimedia IPs such as Display or Video Codecs.
• Experience with ASIC design methodologies for clock domain checks and reset checks.
• Excellent C/C programming and software design skills.

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be responsible for RTL design development of camera and machine learning designs. This includes RTL coding, lint cleanup, SoC IP release flows, architecture, micro-architecture, power, performance and area (PPA) optimizations, test planning collaboration, and coverage reviews and closure for high quality and optimized Core IP deliveries.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $127,000-$187,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
• Perform RTL verification using industry standard methodologies. Participate in test planning and coverage analysis.
• Develop RTL implementations that meet engaged power, performance and area goals.
• Participate in synthesis, timing/power closure and FPGA/silicon bring-up.
• Create tools/scripts to automate tasks and track progress.