Senior Design Veriifcation Engineer

The Artificial Intelligence Silicon Engineering team is seeking a Senior Design Verification Engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge AI designs that can perform complex and high-performance functions in an extremely efficient manner.

We are looking for a Senior Design Verification Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate should be a self-starter who will thrive in this cutting-edge technical environment. You will be part of the design verification team, driving many facets of high performance, high bandwidth designs.

Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.

Responsibilities:

• Perform pre-silicon verification for complex Intellectual Property(IP), including creating testplans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage.
• Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP- or Sub System(SS)-level verification.
• Define verification strategy, requirements, test environments for IP level verification.
• Create testplans and write tests to provide complete features coverage.
• Develop and implement technical solutions to complex quality and design challenges.
• Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage.
• Triage and debug testbench, simulation, and emulation fails.
• Write makefiles and scripts for verification infrastructure.
• Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment.
• Collaborate with teams across sites and geographies.
• Other
  • Embody our Culture and Values

Qualifications:

Required Qualifications:

• 7+ years of technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, or related field AND 4+ years of technical engineering experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, or related field AND 3+ years of technical engineering experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, or related field.
• 6+ years of Technical Engineering Experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals, including scripting languages such as Python/Perl.
• Background in debugging Register Transfer Level(RTL)Verilog designs as well as simulation and/or emulation environments.
• Experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM).

Other Requirements:

• Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred Qualifications:

• 10+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamental
• Verification experience for an IP or SS related to Central Processing Unit(CPUs), Vision Processing Unit(VPUs), Graphics Processing Units(GPUs), Tensor unit, or similar.
• Knowledge of System Verilog class, constraints, coverage and assertions.
• Experience in scripting languages such as Python or Perl.
• Hands-on experience in Formal property verification, formal verification of computational data path designs.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $117,200 - $229,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $153,600 - $250,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Microsoft will accept applications for the role until August 28, 2024.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form .

Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

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