Annapurna Labs builds high-performance hardware and software solutions used in AWS data centers globally. We are seeking an Serdes/PCIE Phy expert with role in the definition, design and validation of AWS next generation ML Chips, Cards and server integration. As a senior member of our platform development team, you will have the outstanding and meaningful opportunity to participate in the design and execution of all Serdes/PCIE topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. The Serdes/PCIE PHY Expert will need to independently work with vendors, understand the settings, write/modify tests, debug and collect data.

Key job responsibilities

As a senior member of the team, you will join a group of hardworking engineers to design and implement innovative next generation machine learning chips and servers. In this position, you will make a real impact in a dynamic, technology focused team. Your work will impact the growing field of machine learning.

You will collaborate with architects, design teams, software engineers to deliver the next generation ML chip. In this position, you will have the opportunity to be responsible for IP integration, 2.5D design, bring up, Characterization and validation.

We are open to hiring candidates to work out of one of the following locations:

Austin, TX, USA

BASIC QUALIFICATIONS

-BS or MS in EE, ECE or CS

-7+ years of experience in Silicon development with -3+ years in SOC/IO/Subsystems

-Deep understanding of Serdes/PCIE at the PHY and controller level including inner workings of PHY component blocks

-Familiar with industry standard protocols such as PCIE

-Experience with test chip characterization and testing compliance

-Experience with post silicon testing include of shmoos including BER, PRBS, Eq settings

-Drive the IP Integration and design of silicon and 2.5D packaging

-Support the physical design team, review clocking and timing constraints

-Drive cross-functional triage effort on complex functional and performance issues

-Take the leadership role in post-silicon bring-up including test plans and execution

-Knowledge of channel electrical and associated tuning parameters, e.g. TX PSET values, RX equalization

-Perform system-level debug and root-cause analysis through bring-up, characterization, validation and production phase

-Experience Working with 3rd party IP vendors

-Strong Firmware development skills within embedded environments

PREFERRED QUALIFICATIONS

-Good leadership skills and ability to multi-task and thrive in a dynamic environment

-Knowledge of PCIE and related protocols

-Good communication skills and interpersonal skills

Amazon is committed to a diverse and inclusive workplace. Amazon is an equal opportunity employer and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status. For individuals with disabilities who would like to request an accommodation, please visit https://www.amazon.jobs/en/disability/us.

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