Summary
At Apple, extraordinary ideas have a way of becoming excellent products and customer experiences very quickly! The industry is accustomed to Apple taping out the SOC's for our various products at a thorough pace. In order to achieve this, Apple's outstanding chip is driven by top notch design engineers who implement various blocks of the chip and deliver high quality components to SoC. This is a high visibility and critically important role and requires close working relationships with many groups and an organized approach to coordinate all tasks in parallel to hit schedules consistently with a quality design!

Key Qualifications
Experience working on FE design that include RTL design, synthesis and QC flows for large scale SOCs.

We pride ourselves on the high quality of our work and consistent record of working on dedication designs in production environments for low power applications will be the key to impress us.

We'll be looking for your expertise in SOC IP integration, sub-system creation and RTL Design for SOC top-level such as IO/PAD-ring, clock and reset distribution and power-management.

Experienced in FE production synthesis with DFT insertion and with expertise in RTL/netlist quality checks including lint, CDC, RDC and logical equivalence.

Extensive experience developing power intent (UPF) for the complex, high-performance and low-power SOC with large number of power islands as well as voltage islands. In addition, your familiarity with DFT (scan, BIST, JATG), timing-closure (STA) and backend related methodologies and tools will be an encouraged asset.

Ability to drive the communication and collaborate across teams is an impactful attribute.

Description
This role will give you ownership of all aspects of design and development of large SOCs, SOC blocks and sub-systems. Handle internal/external IP integration and build sophisticated sub-systems Our engineers design the SOC top level with IPs, sub-systems, PHY-macros, IO/PAD-ring system bus and other infrastructure components for clocking, reset and power-management. We build the integration specs that you develop, run QC checks to ensure quality, create UPF, run synthesis and generate netlist, and close timing for the block. Work closely with Chip Architecture, Design Verification, Physical Design, DFT and power teams to achieve SOC tapeout goals on schedule. Develop and maintain methodology/flows/checks for your design. Work with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process.

Education & Experience
Bachelors Degree + 3 Years of Experience.

---