SoC Power Model Engineer
Austin, Texas
Summary
Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? Do you have a passion for crafting entirely new solutions? Do you love building without precedent?
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing visionary ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned.
You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.
We have an extraordinary opportunity for Power Modeling Engineers.In this highly visible role, you will be responsible for SOC power simulation and power modeling, SOC use case power analysis, and drive the future SOC power optimization.
Key Qualifications
Electrical Engineering background is preferred.
Familiarity with ASIC power analysis and optimization
Familiarity with Verilog and System Verilog.
Proficient with Python scripting*
Familiarity computer architecture, logic and circuits design
Familiarity signal processing is a plus.
Familiarity with SOC design flow and methodology is a plus.
Silicon power measurement experience is a plus.
Strong communication skills are a pre-requisite as the candidate will interface with cross-functional groups.
Description
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers.
The main responsibility of this role is to drive the SOC power modeling and optimization for very power efficient products.
•\tWorking with architects to determine the interesting use-cases to simulate; providing power projection for the future projects based on analysis.
•\tCreating test cases within the design verification team's environment. Working with design teams to determine the correct functionality or enhance functionality for power reduction.
•\tDevelop IP power model on new architecture design, providing power data for performance/power/area tradeoffs.
•\tWork cross functional teams, including architecture, RTL and physical design teams, on improving the power efficiency and power efficiency.
•\tUnderstand interactions of the product at the software and system level that impact power.
Education & Experience
Minimum requirement of a BS degree and a minimum of 3 years of relevant industry experience.
Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? Do you have a passion for crafting entirely new solutions? Do you love building without precedent?
As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing visionary ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned.
You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs.
We have an extraordinary opportunity for Power Modeling Engineers.In this highly visible role, you will be responsible for SOC power simulation and power modeling, SOC use case power analysis, and drive the future SOC power optimization.
Key Qualifications
Electrical Engineering background is preferred.
Familiarity with ASIC power analysis and optimization
Familiarity with Verilog and System Verilog.
Proficient with Python scripting*
Familiarity computer architecture, logic and circuits design
Familiarity signal processing is a plus.
Familiarity with SOC design flow and methodology is a plus.
Silicon power measurement experience is a plus.
Strong communication skills are a pre-requisite as the candidate will interface with cross-functional groups.
Description
Imagine yourself at the center of our SOC design effort, collaborating with all disciplines, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers.
The main responsibility of this role is to drive the SOC power modeling and optimization for very power efficient products.
•\tWorking with architects to determine the interesting use-cases to simulate; providing power projection for the future projects based on analysis.
•\tCreating test cases within the design verification team's environment. Working with design teams to determine the correct functionality or enhance functionality for power reduction.
•\tDevelop IP power model on new architecture design, providing power data for performance/power/area tradeoffs.
•\tWork cross functional teams, including architecture, RTL and physical design teams, on improving the power efficiency and power efficiency.
•\tUnderstand interactions of the product at the software and system level that impact power.
Education & Experience
Minimum requirement of a BS degree and a minimum of 3 years of relevant industry experience.
Created: 2024-08-22
Reference: 200543997
Country: United States
State: Texas
City: Austin
ZIP: 78749
About Apple
Founded in: 1976
Number of Employees: 154000
Website: https://www.apple.com/
Career site: https://www.apple.com/careers/us/
Wikipedia: https://en.wikipedia.org/wiki/Apple_Inc.
Instagram: https://www.instagram.com/apple/
LinkedIn: https://www.linkedin.com/company/apple
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