Technical Lead, ASIC Power Management

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with ASIC design flow in advanced nodes (including synthesis, PNR, STA, and formal verification).
• Experience using EDA power analysis tools like Power-Artist, PT/PTPX, Conformal LP, or Incisive/VCS.

Preferred qualifications:

• Experience in low power digital ASIC design including UPF/CPF, multi-voltage domains, and on-chip power management.
• Experience in transistor level design in advanced finfet technology nodes, including SPICE simulations.
• Experience in post-silicon validation and debug.
• Experience in Verilog, SystemVerilog, and RTL simulation.
• Experience with concurrent power optimization across custom circuit/IP, physical design, RTL, architecture, or package/power delivery domains.
• Scripting experience with languages such as Python, Perl or Tcl.

About the job

As an ASIC Power Management Technical Lead you will architect power solutions for SoCs in advanced technology nodes and enable product definition decisions dependent on power/performance tradeoffs. You will collaborate with circuit design, physical design, RTL, architecture, systems power delivery, and software teams to define and drive power management and optimization methodologies from inception to implementation to sign-off for tapeout and ultimately to manufacture, package, and test.

In this role, you will define the requirements for power management IPs and be responsible for the design, integration, and post-silicon validation of these IPs. You will set power budgets for individual use cases and provide power estimation for blocks and the full chip. You'll collaborate with cross-functional and cross-site teams to drive power reduction across the entire system. As a senior contributor you will provide leadership and mentorship to junior power engineers.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

The US base salary range for this full-time position is $177,000-$266,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Define and drive power methodology for design, verification, and implementation of deep sub micron SoCs.
• Develop innovative power reduction schemes from circuits up through the system level.
• Engage with architects, logic, circuit, and physical designers to define power specs and budgets. Develop accurate power and performance models.
• Own power analysis for blocks and the full-chip level.
• Triage power management issues in pre and post silicon.