Minimum qualifications:

• Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
• 5 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
• Experience scripting in Python or Perl or other related language.
• Experience with Automatic Test Equipment (ATE) test platforms such as Advantest 93K, Teradyne UltraFlex SOC test system.
• Experience with system level testing using Advantest SLT platform.

Preferred qualifications:

• 7 years of experience in the following areas: VLSI technologies, product and test engineering, semiconductor processing.
• Experience with SERDES, PCIe, DDR and Mixed-Signal circuits such as ADC, DAC, PLL, LDO and their performance measurements.
• Knowledge of Design for Test (DFT) techniques and structural tests such as Scan/ATPG, JTAG, and memory BIST.
• Familiarity with advanced packaging such as 2.5d, InFo.
• Familiarity with process technology and how it relates to design and testing Data analysis: wafer sort, final test.
• Familiarity with testing sensors such as PVT sensors, Temp sensors, etc.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $150,000-$223,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

• Work with internal cross-functional teams, external silicon partners, product engineering team, and Intellectual Property (IP) vendors to support structural validate and parametrically characterize the silicon.
• Perform ATE test program development on UFLEX, 93K, or other ATE platforms. Perform ATE loadboard or probe card design for NPI on UFLEX, 93K or other ATE platforms.
• Develop a BenchTop and high volume manufacturing SLT solution working with SLT vendor and internal cross-functional teams.
• Work on IC product bring-up, verification, and characterization on ATE NPI production program release. Troubleshoot on different failure mode and test coverage improvement on ATE.
• Identify new products DPPM correlation, and product correlation between system and ATE.