Summary
Do you love creating elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices!

In this highly visible role, you will be at the heart of the chip design effort collaborating with a variety of fields with critical impact in getting products to millions of customers quickly.

The Graphics Verification Engineer will be responsible for the pre-silicon RTL verification of blocks in low power embedded graphics cores. This includes deep understanding of the micro-architectural details of their block and how it works within the broader GPU design. A strong computer architecture background, preferably in graphics, and a solid foundation in verification methodology will be required to close testing coverage with high confidence.

Key Qualifications
Familiar with Verilog.
Familiar with various HDL simulators and waveform viewers like IES, VCS, DVE, Verdi.
Familiar with Perl, Shell scripting, Makefiles, TCL.
Experience with low-level programming of complex computer systems in C, C++.
Excellent communication skills and ability to learn.
Good knowledge of Computer Architecture; graphics architecture is a plus.
Exposure with code repositories; Perforce is a strong plus.
Experience with verification language such as System Verilog/UVM/OVM is a plus.
Understanding of constrained random verification process, functional and code coverage, assertion methodology is a plus.

Description
•\tPerform unit-level, subsystem, and top verification for logic blocks in graphics processing unit (GPU) designs.
•\tExecute and provide status on test plan items.
•\tPort legacy test bench components in Universal Verification Methodology (UVM) including checkers and monitors.
•\tDevelop unit-level test sequences and handle regressions.
•\tModifying and maintaining testbenches and BFMs.
•\tImplementing stimulus and analyzing coverage.
•\tDebug simulation and silicon GPU failures.
•\tWork closely with design & micro-architecture teams to understand the functional goals of the design.
•\tScripting and software engineering.

Education & Experience
We are looking for candidates with a minimum of BS + 0 years of relevant experience.

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