Senior Logic Design Engineer, Augmented Reality

Fremont, California


Employer: Google
Industry: Hardware Engineering
Salary: Competitive
Job type: Full-Time

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 5 years of experience in logic design and verification, logic synthesis, timing closure, and static timing analysis tools.
  • Experience in Verilog or SystemVerilog HDL for RTL design, verification, and scripting languages (e.g., Python, Perl) for design automation and analysis.


Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with microdisplay or microLED technology.
  • Understanding of digital design fundamentals.
  • Familiarity with low-power design techniques.


About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As the Senior Logic Design Engineer, you will play a pivotal role in the development of full custom microdisplay panels for cutting-edge microLED technology. In this role, you will be responsible for the entire logic design flow from initial concept to silicon validation, ensuring the seamless integration and optimal performance of complex digital circuits within the microdisplay panel.

The Google Augmented Reality team is a diverse group of experts tasked with building the foundations for great immersive computing and building helpful, delightful user experiences. We're focused on making immersive computing accessible to billions of people through mobile devices, and our scope continues to grow and evolve.

The US base salary range for this full-time position is $150,000-$223,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .

Responsibilities

  • Collaborate with multi-functional teams to define microdisplay panel logic architecture and specifications.
  • Design and implement RTL for various digital blocks within the microdisplay panel including control logic, data path, and interfaces.
  • Perform logic synthesis, timing closure, and power optimization to meet design goals.
  • Develop and execute verification plans using simulation and formal verification techniques.
  • Support silicon bring-up and debug, working closely with test and characterization engineers.

Created: 2024-08-22
Reference: 120848362596377286
Country: United States
State: California
City: Fremont
ZIP: 94536


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