Trusted Microelectronics Research & Design Engineer - GTRI - CIPHER - Open Rank

Overview:

The Georgia Tech Research Institute (GTRI) is the nonprofit, applied research division of the Georgia Institute of Technology (Georgia Tech).Founded in 1934 as the Engineering Experiment Station, GTRI has grown to more than 2,900 employees, supporting eight laboratories in over 20 locations around the country and performing more than $940 million of problem-solving research annually for government and industry.GTRI's renowned researchers combine science, engineering, economics, policy, and technical expertise to solve complex problems for the U.S. federal government, state, and industry.

Georgia Tech's Mission and Values

Georgia Tech's mission is to develop leaders who advance technology and improve the human condition. The Institute has nine key values that are foundational to everything we do:

1. Students are our top priority.
2. We strive for excellence.
3. We thrive on diversity.
4. We celebrate collaboration.
5. We champion innovation.
6. We safeguard freedom of inquiry and expression.
7. We nurture the wellbeing of our community.
8. We act ethically.
9. We are responsible stewards.

Over the next decade, Georgia Tech will become an example of inclusive innovation, a leading technological research university of unmatched scale, relentlessly committed to serving the public good; breaking new ground in addressing the biggest local, national, and global challenges and opportunities of our time; making technology broadly accessible; and developing exceptional, principled leaders from all backgrounds ready to produce novel ideas and create solutions with real human impact.

Project/Unit Description

The GTRI Hardware Security and Trust (HST) Division researches microelectronic applications, CAD tools, architectures, and materials to evaluate the security, trust, and reliability of microelectronic devices and the critical systems which rely upon them. HST develops tools and techniques in the areas of assurance, anti-tamper, and reliability for FPGAs, ASICs, SoCs, microcontrollers, and other microelectronics. HST employees are Research Faculty of Georgia Tech and have the opportunity for dual appointments and teaching positions with other departments of the university. HST is a division of GTRI's cyber security lab which contains 300+ engineers and scientists and represents >10% of the total research award funding at Georgia Tech.

Job Purpose

Microelectronics expert to research and contribute to the design, synthesis, characterization, packaging, testing, reliability, security, and trustworthiness of nano-fabricated microelectronic semiconductor devices. This may include research of prototype or commercial semiconductor devices and tools, e.g., ASICs, FPGAs. This position involves close collaboration with a highly technical team of research leaders to accomplish task and program objectives, contribute technically to proposal ideation, and conceive and execute internal research efforts refining core research processes and capabilities. Responsibilities range from CAD/EDA tools development, semiconductor nano-device design, fabrication, and verification, to clean-room equipment utilization. Formal methods and other advanced algorithmic techniques will be leveraged to enable and evaluate security and trustworthiness pre and post-fabrication. The position will utilize a wide range of knowledge from semiconductor physics to micro/nano synthesis and fabrication tools, and develop novel techniques, algorithms, and tools to evaluate CAD/EDA flows, architectures, materials, and fabricated devices with new properties and features.

Key Responsibilities

• Design and execute experiments, or create custom simulations to determine physical parameters/properties and behaviors of microelectronic semiconductor devices, and perform advanced data analysis on the results of measurements and/or simulations
• Design firmware/software with advanced non-standard microelectronic design EDA tools (e.g. TORC, RapidWright, NextPNR, VPR, Yosys)
• Design advanced algorithms covering formal verification, graph analysis, data analysis, clustering, and more
• Utilize advanced microelectronics laboratory equipment (probe stations, X-ray, CT Scanners) to support design, analysis, and verification tasks
• Develop and maintain expertise in a combination of the following languages: Verilog, VHDL, Python, C++, Rust, Kotlin, and Java (or similar)
• Contribute multiple sections of technical reports and presentations
• Contribute to white papers and competitive proposals
• Present research and progress to customers or at working groups

Additional Responsibilities

• Research methodologies using novel combinations of commercial, open-source, and custom tools to implement security enhancements to standard FPGA/ASIC design, verification, and hardware testing practices
• Utilize analysis techniques involving low-level (RTL and gate) design inspection, simulation, formal methods, and bench testing to identify and characterize security and trust concerns of existing designs
• Execute experiments using custom devices, PCBs, and/or simulations to characterize physical parameters, properties, and behaviors of microelectronic semiconductor devices

Required Minimum Qualifications

• Strong understanding of embedded systems, hardware design, digital logic design, and various microelectronic architectures
• Competency designing hardware leveraging at least one industry-standard HDL language (i.e., Verilog, SystemVerilog, VHDL)
• Experience working with at least one major FPGA/ASIC vendor design tool suite (i.e., Xilinx Vivado, Altera/Intel Quartus, Microsemi Libero, Cadence, Synopsys)

Preferred Qualifications

• Active Top Secret Clearance
• FPGA/ASIC design experience with common hardware interfaces (e.g., UART, SPI, I2C), data flow (e.g., FIFOs, clock domain crossing), and bus protocols (e.g., AXI, AMBA)
• Experience performing verification of hardware designs leveraging industry-standard tools and methodologies such as ModelSim/Questa, SystemVerilog, UVM
• Experience with advanced verification techniques such as DO-254, verification planning and tracking, code coverage, equivalency checking, formal property checking (e.g., SVA, PSL), linting, clock-domain-crossing checking
• Experience with hardware fault analysis and mitigation methods for high-reliability or safety-critical systems
• Experience with a high-level scripting language such as Python, TCL
• Hands-on experience with hardware testing, troubleshooting, and embedded hardware/software integration using general laboratory test equipment such as oscilloscopes and logic analyzers
• Comfortable working in a Linux environment

Travel Requirements

Education and Length of Experience

This position vacancy is an open-rank announcement. The final job offer will be dependent on candidate qualifications in alignment with Research Faculty Extension Professional ranks as outlined in section 3.2.1 of the Georgia Tech Faculty Handbook

• 2 years of related experience with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Mathematics, or similar technical area
• 0 years of related experience with a Masters' degree in Electrical Engineering, Computer Engineering, Computer Science, Physics, Mathematics, or similar technical area

U.S. Citizenship Requirements

Due to our research contracts with the U.S. federal government, candidates for this position must be U.S. Citizens.

Clearance Type Required

Candidates must be able to obtain and maintain an active security clearance.

Benefits at GTRI

Comprehensive information on currently offered GTRI benefits, including Health & Welfare, Retirement Plans, Tuition Reimbursement, Time Off, and Professional Development, can be found through this link: https://benefits.hr.gatech.edu/.

Equal Employment Opportunity

The Georgia Institute of Technology (Georgia Tech) is an Equal Employment Opportunity Employer. The University is committed to maintaining a fair and respectful environment for all. To that end, and in accordance with federal and state law, Board of Regents policy, and University policy, Georgia Tech provides equal opportunity to all faculty, staff, students, and all other members of the Georgia Tech community, including applicants for admission and/or employment, contractors, volunteers, and participants in institutional programs, activities, or services. Georgia Tech complies with all applicable laws and regulations governing equal opportunity in the workplace and in educational activities.

Georgia Tech prohibits discrimination, including discriminatory harassment, on the basis of race, ethnicity, ancestry, color, religion, sex (including pregnancy), sexual orientation, gender identity, gender expression, national origin, age, disability, genetics, or veteran status in its programs, activities, employment, and admissions. This prohibition applies to faculty, staff, students, and all other members of the Georgia Tech community, including affiliates, invitees, and guests. Further, Georgia Tech prohibits citizenship status, immigration status, and national origin discrimination in hiring, firing, and recruitment, except where such restrictions are required in order to comply with law, regulation, executive order, or Attorney General directive, or where they are required by Federal, State, or local government contract.

USG Core Values Statement

The University System of Georgia is comprised of our 26 institutions of higher education and learning as well as the System Office. Our USG Statement of Core Values are Integrity, Excellence, Accountability, and Respect. These values serve as the foundation for all that we do as an organization, and each USG community member is responsible for demonstrating and upholding these standards. More details on the USG Statement of Core Values and Code of Conduct are available in USG Board Policy 8.2.18.1.2 and can be found on-line at https://www.usg.edu/policymanual/section8/C224/#p8.2.18_personnel_conduct.

Additionally, USG supports Freedom of Expression as stated in Board Policy 6.5 Freedom of Expression and Academic Freedom found on-line at https://www.usg.edu/policymanual/section6/C2653.

Posted: 08/07/2024
Closes: 09/07/2024