Meta is hiring ASIC Design Engineers within our Infrastructure organization to build cutting edge machine learning ASICs, capable of world class Inference and Training performance. We are looking for talented individuals with deep experience that span one or more of the key areas required to build successful world-class complex SoC and IP for data center applications.

ASIC Engineer, Design Responsibilities

• Architecture exploration.


• Micro-architecture development.


• RTL development using Verilog, System Verilog and HLS.


• Soft and hard IP configuration and integration.


• Collaboration with verification and emulation teams in test plan development and debug.


• Collaboration with implementation team to close the design on timing and power.

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.


• 5+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration.

Preferred Qualifications

• Experience in data path development.


• Experience with Synthesis and Timing Closure.

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