CPU Physical Design Engineer

Summary
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products!

Apple's Silicon Engineering Group (SEG) is hiring hardworking engineers for CPU block-level physical design.

Key Qualifications
Minimum BS and 10+ years of relevant industry experience
Strong electrical engineering fundamentals in logic design, digital circuits, and deep sub-micron technology along with timing, power, and area implications
Proficiency in using industry standard logic Synthesis, PnR, STA and Power analysis tools along with timing budgeting, floor-planing, and physical integration and verification to converge complex designs
Solid understanding of low power, high frequency physical design techniques leveraging advanced syn/PnR tool features and best in class physical design methodology
Programming and scripting ability (Perl, TCL) with strong fundamentals
Ability to work independently and/or lead a physical design partition in collaboration with x-functional teams
Excellent communication and interpersonal skills

Description
As a CPU Physical Design Engineer you will drive or participate in the following:

- Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA goals

- Will be responsible for block-level physical design delivery along with closure of backend flows, electrical requirements and improving silicon yield

- Will work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design

- Will work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability

- Will work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA

Education & Experience
Minimum BS and 10+ years of relevant industry experience

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