FPGA/ASIC Design Engineer

Chipton-Ross is seeking 2 (two) FPGA/ASIC Design Engineers for a contract opportunity in Camden, NJ

From Manager: FPGA Designer, Vivado, Ethernet, VHDL. This is a contract to direct hire posiition. Hourly Pay Rate may exceed $125 for a great candidate..

RESPONSIBILITIES:
The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems. This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security. Develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high speed protocols- NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs. Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux.

DESIRED REQUIREMENTS:
• High Level Synthesis (HLS) with Vivado,
• Embedded SW C++ (OOP) and System Verilog Assertions (SVA)
• Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet)

HARD REQUIREMENTS:
• At least 3 year experience with proven track record of implementing complex algorithms targeting ASIC/FPGAs
• Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.
• Proficiency in VHDL and FPGA design/debug - Xilinx FPGA / Vivado
• Excellent Analytical/Debug skills
• Good verbal, written, and presentation skills

EDUCATION:
• Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred.
**Education MUST be accredited**

SHIFT:
Full-Time
1st Shift
08:00am-05:00pm

MISCELLANEOUS:
Applicants responding to this position will be subject to a government security investigation and must meet eligibility requirements by currently possessing the ability to view classified government information.