Graphics Design Verification Engineer

Summary
Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices.

The Graphics Design Verification Engineer will be responsible for the unit level pre-silicon RTL verification of embedded graphics IP. This includes developing a deep understanding of the micro-architectural details of relevant units and the greater GPU design. A strong computer architecture background, and solid software skills are key attributes to contributing to the Graphics IP verification effort. Exposure to graphics concepts is a plus but not required.

Key Qualifications
The ideal candidate will have minimum 10 years of relevant experience including:
Experience developing test plans and testbenches for advanced hardware designs
Experience driving verification effort from specification to tapeout
Experience with SystemVerilog or expertise in object-oriented languages such as C++
Expertise in common verification methodologies such as UVM or OVM
Experience with HDL simulators and waveform viewers
Experience with Python, Ruby or Perl; developing tools for workflow automation
Experience working under strict schedule deadlines with the ability to manage multiple priorities
Excellent communication skills and ability to collaborate

Description
- Develop verification plans in coordination with design leads and architects
- Create and maintain verification test bench components and environments
- Develop comprehensive constrained random test suites
- Run simulations and debug design and environment issues
- Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes
- Create automated verification flows for block verification
- Apply knowledge of hardware description languages (VHDL/Verilog), and logic simulators to verify complex designs
- Influence other block and core level engineers to innovate seamless verification flows

Education & Experience
BS + minimum of 10 years of experience

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