Senior Low power logic design Engineer
Cupertino, California
Summary
Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC/Power architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, Power modeling / correlation and FW/SW engineering.
In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly. Will you join us and do the work of your life here?
Key Qualifications
We'd like you to have:
Proved track record in power/clock management logic design
Proficiency in Verilog language
SoC level power management logic verification and debug experience
Deep understanding of ASIC low power design techniques
Knowledge of CDC, RDC and UPF and its VCLP checker
Strong problem solving
Proficiency in scripting languages, e.g. Unix shell, Perl or Python
SoC top-level integration experience is a plus
SW team support experience is a plus
System architecture knowledge is a plus
Post-silicon debug experience is a plus
Description
In this role, you will be responsible for designing power management logics for complex wireless communication SoCs, including:
- Define and write specs to cover SOC power management features to meet product requirements
- Implement power management logic
- Work with DV, FPGA and other teams to verify power management logics
- Work with Power team for power analysis work
- Post silicon power management feature debug
- Support power team performing power correlation
Education & Experience
BS and 10+ years of relevant industry experience
Additional Requirements
Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient / low power design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC/Power architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, Power modeling / correlation and FW/SW engineering.
In this highly visible role, you will be at the center of a silicon design group with a critical impact on getting functional products to hundreds of millions of customers quickly. Will you join us and do the work of your life here?
Key Qualifications
We'd like you to have:
Proved track record in power/clock management logic design
Proficiency in Verilog language
SoC level power management logic verification and debug experience
Deep understanding of ASIC low power design techniques
Knowledge of CDC, RDC and UPF and its VCLP checker
Strong problem solving
Proficiency in scripting languages, e.g. Unix shell, Perl or Python
SoC top-level integration experience is a plus
SW team support experience is a plus
System architecture knowledge is a plus
Post-silicon debug experience is a plus
Description
In this role, you will be responsible for designing power management logics for complex wireless communication SoCs, including:
- Define and write specs to cover SOC power management features to meet product requirements
- Implement power management logic
- Work with DV, FPGA and other teams to verify power management logics
- Work with Power team for power analysis work
- Post silicon power management feature debug
- Support power team performing power correlation
Education & Experience
BS and 10+ years of relevant industry experience
Additional Requirements
- Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.
Created: 2024-09-09
Reference: 200517166
Country: United States
State: California
City: Cupertino
About Apple
Founded in: 1976
Number of Employees: 154000
Website: https://www.apple.com/
Career site: https://www.apple.com/careers/us/
Wikipedia: https://en.wikipedia.org/wiki/Apple_Inc.
Instagram: https://www.instagram.com/apple/
LinkedIn: https://www.linkedin.com/company/apple
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