Meta is looking for an experienced Silicon Packaging design Engineer for its Ecosystem and Technical Operation team to support the development of custom Silicon for Infrastructure as well as to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging technology to support the development of custom silicon and looking for expertise in hardware development and integration of machine learning clusters, both server and fabric with focus on the impact they can create as part of a world-class engineering team.

Silicon Packaging Design Engineer Responsibilities

• Perform package design for advanced custom silicon comprising single-chip/multi-chip and 3D or wafer packaging. This includes: design feasibility studies and analyses, package design/layouts based on silicon chip IO, electrical performance and system ID/form factor requirements


• Participate in silicon architecture/package/PCB/system co-design work collaborating with downstream system design teams and upstream silicon designers to develop holistically optimal solutions


• Co-work with internal silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and substrate vendors


• Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for next generation versions of current products


• Lead package development to establish package manufacturability and reliability


• Collaborate with multi-functional teams with in Meta and define package requirements

Minimum Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.


• 10+ years of experience in advanced silicon packaging design


• Experience in advanced package design and proficient in Cadence Allegro platform tools (PCB Editor, Advanced Package Designer, APD/SiP) or Mentor Xpedition platform tools.


• Basic understanding in one of the SI/PI tools (XtractIM, PowerSI, HFSS, Q3D, etc.), package model extraction, S-parameters and RLGC model.


• Hands of experience in interposer or fanout package design for both organic and inorganic interposer with or without bridges


• Bachelor's degree in Electrical engineering, Materials Engineering, Computer Engineering, relevant technical field, or equivalent practical experience.


• Proven fundamentals in the electrical/material/thermal or mechanical engineering field(s).


• Effective communication skills and experience working effectively with cross-functional teams

Preferred Qualifications

• Master's or PhD degree in Electrical/Materials engineering


• Experience and prior experience of taking products from concept to prototyping and production


• In-depth knowledge of flip chip, 2.5D and 3D and wafer packaging technologies package design


• Familiarity with CAM350/Valor or Calibre and CAD along with experience in package design reviews.


• Knowledge of high-speed layout constraints (crosstalk mitigation, differential pairs, EMI/RFI, PCB/package resonance).


• Solid understanding of Design Rules Check and Design for Manufacturing.

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