Title:Silicon Verification Engineer 5

Location: Mountain View,CA(Hybrid)

Contract:6+ Month

Job Description:

Summary:
The main function of Silicon Verification Engineer is to be a part of the test-plan generation process, creating, testing, and implementing various verification plans.

Job Responsibilities:
• Define, document, and implement a UVM verification environment including agents and scoreboards
• Write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral
• Run tests on RTL and Gate Level Netlists, debug failures to root cause, and recommend fixes
• Support post-silicon verification activities of the products working with design and product teams

Skill set:
System Verilog and C/C++ coding a must
Chip/full system level ASIC Verification skills, and debug skills a must
Debug using waveforms a must, Verdi source level debug a plus
System level knowledge a must
System is defined as a test bench containing {CPU + multi-media engines } with hardware based coherency,
System could be a simulation test bench, emulation test bench or a board
System level knowledge/verification does not mean signal integrity checking, electrical checks, EMC checks, thermal checks, ATPG testing on a board, DFT/DFx testing, static timing analysis, lint checking
Tests will be written in C/C++, compiled for CPU and will be run on simulation/emulation/board unchanged
Block/unit level verification skills using UVM knowledge desirable (not required for the work, but having this knowledge means the candidate has been working on verification in the recent past).

Education/Experience:
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related degree required
• 7-10 years of relevant experience required.

PayRate: $85-90/hr,W2